In accordance with electronic products being developed with compact size, light weight and high efficiency, semiconductor packages have been correspondingly reduced in profile and preferably incorporated with multiple chips to be suitable for use with the electronic products. Such structure with multiple semiconductor chips being mounted in a single package is customarily referred to as a multi-chip semiconductor package, wherein the multiple chips can be vertically stacked on a chip carrier (such as a substrate or lead frame) or individually attached to the substrate. The multi-chip package structure has a primary advantage for providing the semiconductor package with effectively enhanced or multiplied electrical and operational performances, making it suitably used in the highly efficient electronic product.
U.S. Pat. Nos. 5,696,031 and 5,973,403 have disclosed a multi-chip semiconductor package. Referring to FIG. 5, in this semiconductor package, a first chip 21 is mounted on a surface of a substrate 20 in a flip-chip manner that an active surface 210 of the first chip 21 faces downwards and is electrically connected to the substrate 20 via a plurality of solder bumps 22. Then, a second chip 23 is attached to a non-active surface 211 of the first chip 21 and is electrically connected to the substrate 20 via a plurality of bonding wires 24. An encapsulation body 25 is formed on the substrate 20 to encapsulate the first chip 21, second chip 23 and bonding wires 24. Finally, a plurality of solder balls 26 are implanted on an opposite surface of the substrate 20. This completes fabrication of the multi-chip semiconductor package. Since the wire-bonding process performed on the second chip 23 would generate shocks that may cause cracks of the solder bumps 22, an underfill process is carried out between the first chip 21 and the substrate 20 to fill an insulating material (such as a resin material, etc.) in gaps between the adjacent solder bumps 22, so as to enhance the mechanical strength of the solder bumps 22 and prevent them from cracks due to the shocks generated by the wire-bonding process.
However, during the underfill process for the above semiconductor package, the procedure of filling the insulating material may easily contaminate predetermined positions (such as bond fingers) on the substrate for connecting the bonding wires, and the bonding wires cannot be firmly bonded to the contaminated bond fingers, such that the yield of the wire-bonding process and the quality of electrical connection between the second chip and the substrate would be degraded, and the reliability of the entire semiconductor package is thus deteriorated. Moreover, for the second chip that is electrically connected to the substrate via the bonding wires, since the second chip is directly incorporated in the semiconductor package with the quality and yield of the second chip being unknown, a known good die (KGD) issue is produced. In other words, if the second chip not passing a burn-in test incurs quality defects, the entire package having such second chip would fail and the product yield is reduced.
U.S. Patent Publication No. 2004/0113275 has disclosed another multi-chip semiconductor package. As shown in FIG. 6, this semiconductor package allows a first chip 31 to be mounted on a surface of a substrate 30 in a flip-chip manner, wherein an active surface 310 of the first chip 31 faces downwards and is electrically connected to the substrate 30 via a plurality of solder bumps 32. An insulating material (such as a resin material, etc.) is filled in gaps between the adjacent solder bumps 32 using an underfill technique. Then, a land grid array (LGA) package structure 33 is attached to a non-active surface 311 of the first chip 31 in an inverted manner, and a substrate 330 of the LGA package structure 33 is electrically connected to the substrate 30 via a plurality of bonding wires 34. An encapsulation body 35 is formed on the substrate 30 to encapsulate the first chip 31, LGA package structure 33 and bonding wires 34. Finally, a plurality of solder balls 36 are implanted on an opposite surface of the substrate 30. This completes fabrication of the multi-chip semiconductor package.
Although the above fabrication method may solve the KGD problem, the multi-chip semiconductor package shown in FIG. 6 still have the similar drawback to that shown in FIG. 5. As the underfill process is required to fill the gaps between the adjacent solder bumps 32 with the insulating material so as to enhance the mechanical strength of the solder bumps 32 and prevent them from cracks due to shocks during the wire-bonding process, the procedure of filling the insulating material may easily contaminate predetermined positions (such as bond fingers) on the substrate 30 for connecting the bonding wires 34, and the bonding wires 34 cannot be firmly bonded to the contaminated bond fingers, thereby degrading the yield of the wire-bonding process and the quality of electrical connection between the LGA package structure 33 and the substrate 30, as well as deteriorating the reliability of the entire semiconductor package.
Therefore, the problem to be solved here is to provide a multi-chip semiconductor package, which can prevent predetermined positions for electrical connection on a substrate from contamination and eliminate a KGD issue so as to assure the reliability and yield of the semiconductor package.